The final phase in the manufacture of semiconductor devices and especially of planar, mesa and MOS power devices consists of voltage testing on wafer.
The automatic equipment used for this purpose is very often prevented from operating properly by the occurrence of superficial electrical discharges.
This problem is currently avoided by using a testing voltage lower than that at which the device is designed to operate and by putting off the testing at the maximum operating voltage until after the device has been fitted into a plastic or metal casing.
In this way, however, the percentage of rejects gives rise to a heavier economic impact since the loss involves not only the cost of the device on the wafer but also the cost pertaining to its assembly.